A System for Efficiently Self-Reconstructing E-1 1 \over 2 -Track Switch Torus Arrays

I
ISPAN
2000
2000 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '00)
Abstract - A System for Efficiently Self-Reconstructing E-1 1 \over 2 -Track Switch Torus Arrays

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2000 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '00)

Dallas/Richardson, Texas, USA

December 07-December 07

ISBN: 0-7695-0936-3

	ASCII Text	x
	T. Horita, I. Takanami, "A System for Efficiently Self-Reconstructing E-1 1 \over 2 -Track Switch Torus Arrays," Parallel Architectures, Algorithms, and Networks, International Symposium on, pp. 44, 2000 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '00), 2000.

	BibTex	x
	@article{ 10.1109/ISPAN.2000.900260, author = {T. Horita and I. Takanami}, title = {A System for Efficiently Self-Reconstructing E-1 1 \over 2 -Track Switch Torus Arrays}, journal ={Parallel Architectures, Algorithms, and Networks, International Symposium on}, volume = {0}, year = {2000}, issn = {1087-4089}, pages = {44}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISPAN.2000.900260}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Parallel Architectures, Algorithms, and Networks, International Symposium on TI - A System for Efficiently Self-Reconstructing E-1 1 \over 2 -Track Switch Torus Arrays SN - 1087-4089 SP EP A1 - T. Horita, A1 - I. Takanami, PY - 2000 KW - Massively parallel computer KW - Hierarchical interconnection KW - Interconnection networks KW - Wafer scale integration (WSI) KW - 3D stacked implementation KW - Peak number of vertical links VL - 0 JA - Parallel Architectures, Algorithms, and Networks, International Symposium on ER -

T. Horita

I. Takanami

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISPAN.2000.900260

A mesh-connected processor array consists of many similar processing elements (PEs), which can be executed in both parallel and pipeline processing. FOT the implementation of an array of large numbers of processors, it is necessary to consider some fault tolerant issues to enhance the (fabrication-time) yield and the (ran-time) reliability.

Index Terms:

Massively parallel computer, Hierarchical interconnection, Interconnection networks, Wafer scale integration (WSI), 3D stacked implementation, Peak number of vertical links

Citation:

T. Horita, I. Takanami, "A System for Efficiently Self-Reconstructing E-1 1 \over 2 -Track Switch Torus Arrays," ispan, pp.44, 2000 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '00), 2000

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