1996 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '96) The Affect of Cache to Speedup Models Beijing, CHINA June 12-June 14 ISBN: 0-8186-7460-1
Speedup is usually used to reflect the effect of parallel processing systems. But the existed speedup models do not consider about the affect of cache, so the affect of cache to several speedup models is analysed in this paper.
Index Terms:
speedup, cache, performance evaluation
Citation:
Xue Yibo, Chen Lan, Han Chengde, "The Affect of Cache to Speedup Models," ispan, pp.262, 1996 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '96), 1996 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||