loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
38th International Symposium on Multiple Valued Logic (ismvl 2008)
Time-Domain Pre-Emphasis Techniques for Equalization of Multiple-Valued Data
May 22-May 24
ISBN: 978-0-7695-3155-7
ASCII Text
x 
 
Yasushi Yuminaka, Yasunori Takahashi, "Time-Domain Pre-Emphasis Techniques for Equalization of Multiple-Valued Data," Multiple-Valued Logic, IEEE International Symposium on, pp. 20-25, 38th International Symposium on Multiple Valued Logic (ismvl 2008), 2008.
 
 
BibTex
x
 
@article{ 10.1109/ISMVL.2008.40,
author = {Yasushi Yuminaka and Yasunori Takahashi},
title = {Time-Domain Pre-Emphasis Techniques for Equalization of Multiple-Valued Data},
journal ={Multiple-Valued Logic, IEEE International Symposium on},
volume = {0},
year = {2008},
issn = {0195-623X},
pages = {20-25},
doi = {http://doi.ieeecomputersociety.org/10.1109/ISMVL.2008.40},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Multiple-Valued Logic, IEEE International Symposium on
TI - Time-Domain Pre-Emphasis Techniques for Equalization of Multiple-Valued Data
SN - 0195-623X
SP20
EP25
A1 - Yasushi Yuminaka,
A1 - Yasunori Takahashi,
PY - 2008
KW - Pre-emphasis
KW - Equalizer
KW - Multi-valued logic
KW - High-speed interface
VL - 0
JA - Multiple-Valued Logic, IEEE International Symposium on
ER -
 
This paper presents a new equalization technique based on a Pulse-Width Modulation (PWM)??pre-emphasis method which utilizes time-domain information processing to increase the data rate for a given bandwidth of VLSI interconnection. The pre-emphasis method does not change the pulse amplitude as for conventional FIR pre-emphasis, but instead exploits timing resolution. This fits well with recent CMOS technology trends toward higher switching speeds and lower voltage headroom. We discuss new time-domain pre-emphasis techniques especially for multiple-valued data transmission in order to achieve high-speed data transmission in VLSI systems.
Index Terms:
Pre-emphasis, Equalizer, Multi-valued logic, High-speed interface
Citation:
Yasushi Yuminaka, Yasunori Takahashi, "Time-Domain Pre-Emphasis Techniques for Equalization of Multiple-Valued Data," ismvl, pp.20-25, 38th International Symposium on Multiple Valued Logic (ismvl 2008), 2008
Usage of this product signifies your acceptance of the Terms of Use.