38th International Symposium on Multiple Valued Logic (ismvl 2008) Multiple Valued Logic Using 3-State Quantum Dot Gate FETs May 22-May 24 ISBN: 978-0-7695-3155-7
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISMVL.2008.34
This paper presents fundamental logic structures designed using novel quantum dot gate FETs with three-state characteristics. This three-state FET manifests itself as a transistor with a stable "intermediate" state, where the drain current remains constant over a range of input gate voltages due to a change in the threshold voltage over this range. We have developed a simplified circuit model that accounts for this intermediate state. Using this model, we have designed rudimentary logic circuits for use in multiple-valued logic circuits.
Index Terms:
quantum dots, multiple-valued logic
Citation:
John A. Chandy, Faquir C. Jain, "Multiple Valued Logic Using 3-State Quantum Dot Gate FETs," ismvl, pp.186-190, 38th International Symposium on Multiple Valued Logic (ismvl 2008), 2008 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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