A 3/7-Level Mixed-Mode Algorithmic Analog-to-Digital Converter

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38th International Symposium on Multiple Valued Logic (ismvl 2008)

May 22-May 24

ISBN: 978-0-7695-3155-7

	ASCII Text	x
	Kazuki Akutagawa, Kazuya Machida, Takao Waho, "A 3/7-Level Mixed-Mode Algorithmic Analog-to-Digital Converter," Multiple-Valued Logic, IEEE International Symposium on, pp. 174-179, 38th International Symposium on Multiple Valued Logic (ismvl 2008), 2008.

	BibTex	x
	@article{ 10.1109/ISMVL.2008.25, author = {Kazuki Akutagawa and Kazuya Machida and Takao Waho}, title = {A 3/7-Level Mixed-Mode Algorithmic Analog-to-Digital Converter}, journal ={Multiple-Valued Logic, IEEE International Symposium on}, volume = {0}, year = {2008}, issn = {0195-623X}, pages = {174-179}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISMVL.2008.25}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Multiple-Valued Logic, IEEE International Symposium on TI - A 3/7-Level Mixed-Mode Algorithmic Analog-to-Digital Converter SN - 0195-623X SP174 EP179 A1 - Kazuki Akutagawa, A1 - Kazuya Machida, A1 - Takao Waho, PY - 2008 KW - analog-to-digital converter KW - algorithmic KW - multiple-valued KW - redundancy VL - 0 JA - Multiple-Valued Logic, IEEE International Symposium on ER -

Kazuki Akutagawa

Kazuya Machida

Takao Waho

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISMVL.2008.25

A 3/7-level mixed-mode algorithmic analog-to-digital onverter (ADC) is proposed. The operation comprises six phases to obtain the 8-bit resolution. The 3-level mode is used in the first three phases for an accurate conversion, while the 7-level mode is used for the last three phases to improve the sampling speed. Transistor-level simulations assuming 0.18-$\mu $m CMOS technology with a supply voltage of 1.8 V are carried out to estimate the circuit performance. A signal-to-noise ratio of 48.1dB ($\approx $7.7 bit) is obtained at a sampling frequency of 12.8 MHz, which is superior to the results obtained from??conventional 3-level and 7-level algorithmic ADCs.

Index Terms:

analog-to-digital converter, algorithmic, multiple-valued, redundancy

Citation:

Kazuki Akutagawa, Kazuya Machida, Takao Waho, "A 3/7-Level Mixed-Mode Algorithmic Analog-to-Digital Converter," ismvl, pp.174-179, 38th International Symposium on Multiple Valued Logic (ismvl 2008), 2008

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