38th International Symposium on Multiple Valued Logic (ismvl 2008) High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit May 22-May 24 ISBN: 978-0-7695-3155-7
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISMVL.2008.12
A high-speed timing verification scheme using delay tables is proposed for a large-scaled multiple-valued current-mode (MVCM) circuit. A multi-level input-signal transition in the MVCM circuit is decomposed of binary signal transitions whose behaviors are represented using delay tables as higher abstracted description than transistor-level one. This high-level abstraction makes it possible to greatly improve the timing-verification speed of the MVCM circuit. It is demonstrated that the timing-verification speed for a 32-digit radix-2 signed-digit adder in the proposed method is about 1000-times faster than that in a conventional HSPICE-based approach with maintaining high delay-estimation accuracy.
Index Terms:
Static timing analysis, Verilog-AMS, Look-up table
Citation:
Tasuku Nagai, Naoya Onizawa, Takahiro Hanyu, "High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit," ismvl, pp.70-75, 38th International Symposium on Multiple Valued Logic (ismvl 2008), 2008 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb