38th International Symposium on Multiple Valued Logic (ismvl 2008) Design of High-Performance Quaternary Adders Based on Output-Generator Sharing May 22-May 24 ISBN: 978-0-7695-3155-7
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISMVL.2008.11
Simple implementations of quaternary full adders are proposed for a high-performance multi-processor which consists of many processing elements (PEs).Arbitrary quaternary functions are represented by the combination of input-value conversion and several quaternary output generations.The use of appropriate input-value conversion makes it possible to reduce the number of output generators, which improves the performance of the resulting quaternary full adders.For example, two kinds of single PEs including a quaternary full adder and two flip-flops are implemented using the proposed method and their efficiencies are demonstrated in terms of delay and power dissipation in comparison with those of a corresponding binary CMOS implementation.
Index Terms:
Carry pre-addition, Current-mode circuit, Differential-pair circuitry, Voltage-mode circuit, Transfer-gate circuitry
Citation:
Hirokatsu Shirahama, Takahiro Hanyu, "Design of High-Performance Quaternary Adders Based on Output-Generator Sharing," ismvl, pp.8-13, 38th International Symposium on Multiple Valued Logic (ismvl 2008), 2008 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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