36th International Symposium on Multiple-Valued Logic (ISMVL'06) A Novel Balanced Ternary Adder Using Recharged Semi-Floating Gate Devices Singapore May 17-May 20 ISBN: 0-7695-2532-6
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISMVL.2006.7
This paper presents a novel voltage mode Balanced Ternary Adder (BTA), implemented with Recharged Semi- Floating Gate Devices. By using balanced ternary notation, it possible to take advantage of carry free addition, which is exploited in designing a fast adder cell. The circuit operates at 1 GHz clock frequency. The supply voltage is only 1.0 Volt. The circuit is simulated by using Cadence R Analog Design Environment, with CMOS090 process parameters, a 90nm General Purpose Bulk CMOS Process from STMicroelectronics with 7 metal layers. All the capacitors are metal plate capacitors, based on vertical coupling capacitance between stacked metal plates.
Citation:
Henning Gundersen, Yngvar Berg, "A Novel Balanced Ternary Adder Using Recharged Semi-Floating Gate Devices," ismvl, pp.18, 36th International Symposium on Multiple-Valued Logic (ISMVL'06), 2006 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||