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36th International Symposium on Multiple-Valued Logic (ISMVL'06)
The new architecture of radix-4 Chinese abacus adder
Singapore
May 17-May 20
ISBN: 0-7695-2532-6
ASCII Text
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Shu-Chung Yi, Kun-Tse Lee, Jin-Jia Chen, Chien-Hung Lin, Chuen-Ching Wang, Chin-Fa Hsieh, Chih-Yung Lu, "The new architecture of radix-4 Chinese abacus adder," Multiple-Valued Logic, IEEE International Symposium on, pp. 12, 36th International Symposium on Multiple-Valued Logic (ISMVL'06), 2006.
 
 
BibTex
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@article{ 10.1109/ISMVL.2006.41,
author = {Shu-Chung Yi and Kun-Tse Lee and Jin-Jia Chen and Chien-Hung Lin and Chuen-Ching Wang and Chin-Fa Hsieh and Chih-Yung Lu},
title = {The new architecture of radix-4 Chinese abacus adder},
journal ={Multiple-Valued Logic, IEEE International Symposium on},
volume = {0},
year = {2006},
issn = {0195-623X},
pages = {12},
doi = {http://doi.ieeecomputersociety.org/10.1109/ISMVL.2006.41},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Multiple-Valued Logic, IEEE International Symposium on
TI - The new architecture of radix-4 Chinese abacus adder
SN - 0195-623X
SP
EP
A1 - Shu-Chung Yi,
A1 - Kun-Tse Lee,
A1 - Jin-Jia Chen,
A1 - Chien-Hung Lin,
A1 - Chuen-Ching Wang,
A1 - Chin-Fa Hsieh,
A1 - Chih-Yung Lu,
PY - 2006
KW - null
VL - 0
JA - Multiple-Valued Logic, IEEE International Symposium on
ER -
 
Shu-Chung Yi, National Changhua University of Education, Changhua, Taiwan
Kun-Tse Lee, National Changhua University of Education, Changhua, Taiwan
Jin-Jia Chen, National Changhua University of Education, Changhua, Taiwan
Chien-Hung Lin, National Changhua University of Education, Changhua, Taiwan
Chuen-Ching Wang, National Changhua University of Education, Changhua, Taiwan
Chin-Fa Hsieh, China Institute of Technology, Taipei, Taiwan
Chih-Yung Lu, China Institute of Technology, Taipei, Taiwan
In this paper, we present a new architecture of Chinese abacus adder. As high radix of adder may reduce the number of carry propagation, the proposed Chinese abacus adder may achieve high-speed operation. The simulation results of our work are compared with CLA (Carry Look-ahead) adder. The delay of the 8-bit abacus adders are 22%, 17%, and 14% less than those of CLA adders for 0.35?m, 0.25?m, and 0.18?m technologies, respectively. The power consumption of the abacus adders are 30%, 34%, and 60% less than those of CLA adders for 0.35?m, 0.25?m, and 0.18?m technologies, respectively. The use of Chinese abacus approach results a competitive technique with respect to conventional fast adder.
Citation:
Shu-Chung Yi, Kun-Tse Lee, Jin-Jia Chen, Chien-Hung Lin, Chuen-Ching Wang, Chin-Fa Hsieh, Chih-Yung Lu, "The new architecture of radix-4 Chinese abacus adder," ismvl, pp.12, 36th International Symposium on Multiple-Valued Logic (ISMVL'06), 2006
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