36th International Symposium on Multiple-Valued Logic (ISMVL'06) On Designs of Radix Converters Using Arithmetic Decompositions Singapore May 17-May 20 ISBN: 0-7695-2532-6
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISMVL.2006.31
In arithmetic circuits for digital signal processing, radixes other than two are often used to make circuits faster. In such cases, radix converters are necessary. However, in general, radix converters tend to be complex. This paper considers design methods for p-nary to binary converters. It introduces a new design technique called arithmetic decomposition. It also compares the amount of hardware and performance of radix converters implemented on FPGAs.
Citation:
Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura, "On Designs of Radix Converters Using Arithmetic Decompositions," ismvl, pp.3, 36th International Symposium on Multiple-Valued Logic (ISMVL'06), 2006 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||