On Designs of Radix Converters Using Arithmetic Decompositions

I
ISMVL
2006
36th International Symposium on Multiple-Valued Logic (ISMVL'06)
Abstract - On Designs of Radix Converters Using Arithmetic Decompositions

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36th International Symposium on Multiple-Valued Logic (ISMVL'06)

Singapore

May 17-May 20

ISBN: 0-7695-2532-6

	ASCII Text	x
	Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura, "On Designs of Radix Converters Using Arithmetic Decompositions," Multiple-Valued Logic, IEEE International Symposium on, pp. 3, 36th International Symposium on Multiple-Valued Logic (ISMVL'06), 2006.

	BibTex	x
	@article{ 10.1109/ISMVL.2006.31, author = {Yukihiro Iguchi and Tsutomu Sasao and Munehiro Matsuura}, title = {On Designs of Radix Converters Using Arithmetic Decompositions}, journal ={Multiple-Valued Logic, IEEE International Symposium on}, volume = {0}, year = {2006}, issn = {0195-623X}, pages = {3}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISMVL.2006.31}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Multiple-Valued Logic, IEEE International Symposium on TI - On Designs of Radix Converters Using Arithmetic Decompositions SN - 0195-623X SP EP A1 - Yukihiro Iguchi, A1 - Tsutomu Sasao, A1 - Munehiro Matsuura, PY - 2006 KW - null VL - 0 JA - Multiple-Valued Logic, IEEE International Symposium on ER -

Yukihiro Iguchi, Meiji University, Kawasaki 214-8571, Japan

Tsutomu Sasao, Kyushu Institute of Technology, Iizuka , Japan

Munehiro Matsuura, Kyushu Institute of Technology, Iizuka , Japan

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISMVL.2006.31

In arithmetic circuits for digital signal processing, radixes other than two are often used to make circuits faster. In such cases, radix converters are necessary. However, in general, radix converters tend to be complex. This paper considers design methods for p-nary to binary converters. It introduces a new design technique called arithmetic decomposition. It also compares the amount of hardware and performance of radix converters implemented on FPGAs.

Citation:

Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura, "On Designs of Radix Converters Using Arithmetic Decompositions," ismvl, pp.3, 36th International Symposium on Multiple-Valued Logic (ISMVL'06), 2006

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