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36th International Symposium on Multiple-Valued Logic (ISMVL'06)
Design of a Microprocessor Datapath Using Four-Valued Differential-Pair Circuits
Singapore
May 17-May 20
ISBN: 0-7695-2532-6
Akira Mochizuki, Tohoku University, Japan
Takeshi Kitamura, Tohoku University, Japan
Hirokatsu Shirahama, Tohoku University, Japan
Takahiro Hanyu, Tohoku University, Japan
New four-valued logic and static storage components using differential-pair circuits (DPCs) are proposed for a high-performance microprocessor datapath. The DPCbased circuit makes a signal-voltage swing small yet the current-driving capability large, and generates complementary outputs. Both a four-valued comparator and a binary static latch can be merged into a simple DPC-based circuit structure, which achieves low-power dissipation and small chip area while maintaining high-speed switching. As a typical application, a 32-bit microprocessor datapath with five pipelining stages is implemented using the proposed circuit technique in 0.18?m CMOS, and its advantages are demonstrated in comparison with a corresponding CMOS implementation.
Citation:
Akira Mochizuki, Takeshi Kitamura, Hirokatsu Shirahama, Takahiro Hanyu, "Design of a Microprocessor Datapath Using Four-Valued Differential-Pair Circuits," ismvl, pp.14, 36th International Symposium on Multiple-Valued Logic (ISMVL'06), 2006
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