36th International Symposium on Multiple-Valued Logic (ISMVL'06)
Design Methods for Multiple-Valued Input Address Generators
Singapore
May 17-May 20
ISBN: 0-7695-2532-6
A multiple-valued input address generator produces a unique address given a multiple-valued input data vector. This paper presents methods to realize multiple-valued input address generators by multi-level networks of p-input q-output memories. It shows a method to simplify the address generators using an auxiliary memory.