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36th International Symposium on Multiple-Valued Logic (ISMVL'06)
Design Methods for Multiple-Valued Input Address Generators
Singapore
May 17-May 20
ISBN: 0-7695-2532-6
ASCII Text
x 
 
Tsutomu Sasao, "Design Methods for Multiple-Valued Input Address Generators," Multiple-Valued Logic, IEEE International Symposium on, pp. 1, 36th International Symposium on Multiple-Valued Logic (ISMVL'06), 2006.
 
 
BibTex
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@article{ 10.1109/ISMVL.2006.17,
author = {Tsutomu Sasao},
title = {Design Methods for Multiple-Valued Input Address Generators},
journal ={Multiple-Valued Logic, IEEE International Symposium on},
volume = {0},
year = {2006},
issn = {0195-623X},
pages = {1},
doi = {http://doi.ieeecomputersociety.org/10.1109/ISMVL.2006.17},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Multiple-Valued Logic, IEEE International Symposium on
TI - Design Methods for Multiple-Valued Input Address Generators
SN - 0195-623X
SP
EP
A1 - Tsutomu Sasao,
PY - 2006
KW - null
VL - 0
JA - Multiple-Valued Logic, IEEE International Symposium on
ER -
 
Tsutomu Sasao, Kyushu Institute of Technology, Japan
A multiple-valued input address generator produces a unique address given a multiple-valued input data vector. This paper presents methods to realize multiple-valued input address generators by multi-level networks of p-input q-output memories. It shows a method to simplify the address generators using an auxiliary memory.
Citation:
Tsutomu Sasao, "Design Methods for Multiple-Valued Input Address Generators," ismvl, pp.1, 36th International Symposium on Multiple-Valued Logic (ISMVL'06), 2006
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