A Two-Bit-per-Cell Content-Addressable Memory Using Single-Electron Transistors

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35th International Symposium on Multiple-Valued Logic (ISMVL'05)

University of Calgary, Canada

May 19-May 21

ISBN: 0-7695-2336-6

	ASCII Text	x
	Katsuhiko Degawa, Takafumi Aoki, Hiroshi Inokawa, Tatsuo Higuchi, Yasuo Takahashi, "A Two-Bit-per-Cell Content-Addressable Memory Using Single-Electron Transistors," Multiple-Valued Logic, IEEE International Symposium on, pp. 32-38, 35th International Symposium on Multiple-Valued Logic (ISMVL'05), 2005.

	BibTex	x
	@article{ 10.1109/ISMVL.2005.6, author = {Katsuhiko Degawa and Takafumi Aoki and Hiroshi Inokawa and Tatsuo Higuchi and Yasuo Takahashi}, title = {A Two-Bit-per-Cell Content-Addressable Memory Using Single-Electron Transistors}, journal ={Multiple-Valued Logic, IEEE International Symposium on}, volume = {0}, year = {2005}, issn = {0195-623X}, pages = {32-38}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISMVL.2005.6}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Multiple-Valued Logic, IEEE International Symposium on TI - A Two-Bit-per-Cell Content-Addressable Memory Using Single-Electron Transistors SN - 0195-623X SP32 EP38 A1 - Katsuhiko Degawa, A1 - Takafumi Aoki, A1 - Hiroshi Inokawa, A1 - Tatsuo Higuchi, A1 - Yasuo Takahashi, PY - 2005 KW - null VL - 0 JA - Multiple-Valued Logic, IEEE International Symposium on ER -

Katsuhiko Degawa, Tohoku University, Japan

Takafumi Aoki, Tohoku University, Japan

Hiroshi Inokawa, NTT Corporation, Japan

Tatsuo Higuchi, Tohoku Institute of Technology, Japan

Yasuo Takahashi, Hokkaido University, Japan

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISMVL.2005.6

This paper presents a circuit design of a two-bit-percell Content-Addressable Memory (CAM) using Single-Electron Transistors (SETs). The key ideas of the proposed CAM architecture are (i) four-level data storage function implementing by a SET-based static memory cell and (ii) four-level data matching function employing periodic drain-current characteristics of SETs with dynamic phase-shift control. A simple multi-gate SET can be used to realize four-level data matching within a compact CAM cell circuit. As a result, the proposed two-bit-per-cell CAM architecture reduces the number of transistors to 1/3 compared with the conventional CAM architecture.

Citation:

Katsuhiko Degawa, Takafumi Aoki, Hiroshi Inokawa, Tatsuo Higuchi, Yasuo Takahashi, "A Two-Bit-per-Cell Content-Addressable Memory Using Single-Electron Transistors," ismvl, pp.32-38, 35th International Symposium on Multiple-Valued Logic (ISMVL'05), 2005

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