35th International Symposium on Multiple-Valued Logic (ISMVL'05) Three Dimensional Multi-Valued Design in Nanoscale Integrated Circuits University of Calgary, Canada May 19-May 21 ISBN: 0-7695-2336-6
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISMVL.2005.49
Novel three-dimensional (3D) nanoscale integrated circuits (nanoICs) are examined in this paper. These nanoICs are synthesized utilizing aggregated 3D neuronal-hypercells (ℵ-hypercells) with multi-terminal electronic nanodevices. The proposed nanodevices ensure multi-valued inputoutput characteristic that lead to a direct technological solution of multi-valued logic synthesis problem. Super-high-performance computing architectures and memories can be devised (synthesized), designed and optimized. At the system-level, we examine nanoICs as networked aggregated 3D ℵ-hypercells. In particular, scalable 3D ℵ-hypercell topologies are under consideration. These ℵ-hypercells integrate interconnected functional multi-terminal electronic nanodevices that implement logic functions. The proposed nanoICs platform suits the envisioned cognizant computing ensuring preeminent information processing and immense memory.
Citation:
Sergey Edward Lyshevski, "Three Dimensional Multi-Valued Design in Nanoscale Integrated Circuits," ismvl, pp.82-87, 35th International Symposium on Multiple-Valued Logic (ISMVL'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||