35th International Symposium on Multiple-Valued Logic (ISMVL'05) Signed-digit CMOS (SD-CMOS) Logic Circuits with Dynamic Operation University of Calgary, Canada May 19-May 21 ISBN: 0-7695-2336-6
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISMVL.2005.44
This paper proposes a design for signed-digit CMOS (SD-CMOS) basic circuits, such as a driver circuit, an inverter circuit, and a full-adder circuit, and describes a parallel multiplier circuit capable of high-speed operation with a time of about 10 nsec independent of the bit length. The proposed CMOS basic circuits utilize a multi-voltage power supply to enable dynamic operation with pre-charged output terminals at signal level 0 (VDD1). This design methodology is applicable to arithmetic circuits for highly accurate, high-speed processors.
Citation:
Hideki Fukuda, "Signed-digit CMOS (SD-CMOS) Logic Circuits with Dynamic Operation," ismvl, pp.144-151, 35th International Symposium on Multiple-Valued Logic (ISMVL'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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