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35th International Symposium on Multiple-Valued Logic (ISMVL'05)
Radix Converters: Complexity and Implementation by LUT Cascades
University of Calgary, Canada
May 19-May 21
ISBN: 0-7695-2336-6
Tsutomu Sasao, Kyushu Institute of Technology, Japan
In digital signal processing, we often use higher radix system to achieve high-speed computation. In such cases, we require radix converters. This paper considers the design of LUT cascades that convert p-nary numbers to q-nary numbers. In particular, we derive several upper bounds on the column multiplicities of decomposition charts that represent radix converters. From these, we can estimate the size of LUT cascades to realize radix converters. These results are useful to design compact radix converters, since these bounds show strategies to partition the outputs into groups.
Citation:
Tsutomu Sasao, "Radix Converters: Complexity and Implementation by LUT Cascades," ismvl, pp.256-263, 35th International Symposium on Multiple-Valued Logic (ISMVL'05), 2005
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