35th International Symposium on Multiple-Valued Logic (ISMVL'05)
Multiple-Valued VLSI Architecture for Intra-Chip Packet Data Transfer
University of Calgary, Canada
May 19-May 21
ISBN: 0-7695-2336-6
A packet data transfer scheme is introduced for intrachip data transfer to solve an interconnection problem. A protocol suitable for intra-chip data transfer is proposed to make a router as simple as possible. The total number of packets in a micronetwork can be reduced by multiplexing two binary packets into a single multiple-valued packet, which makes the micronetwork throughput very high. The multiplexing can be realized by liner summation of two packets in current-mode logic. Moreover, multiple-valued source-coupled logic is introduced in the router circuit. Thus, we can design the very high-speed micronetwork using current-mode multiple-valued logic.
Citation:
Tomoaki Hasegawa, Yuya Homma, Michitaka Kameyama, "Multiple-Valued VLSI Architecture for Intra-Chip Packet Data Transfer," ismvl, pp.114-119, 35th International Symposium on Multiple-Valued Logic (ISMVL'05), 2005