35th International Symposium on Multiple-Valued Logic (ISMVL'05) Multiple-Valued Logic Approach for a Systolic^2 AB Circuit in Galois Field University of Calgary, Canada May 19-May 21 ISBN: 0-7695-2336-6
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISMVL.2005.30
In public key cryptosystems and error-correcting codes over Galois fields, the AB^2 operation is an efficient basic operation. The current paper presents the use of multiple-valued logic (MVL) approach to minimize the systolic architecture of AB^2 algorithm over binary Galois fields. The design is composed of four basic cells connected in a pipelined fashion. The circuit has been simulated using Affirma Analog Circuit Design Environment tool supplied by Cadence, and it has shown to perform correctly. The quaternary circuit for GF((2^2 )^2 ) shows a significant amount of savings in both transistor count and the number of connections compared to the one that uses the binary field GF(2⁴).
Citation:
Nabil Abu-Khader, Pepe Siy, "Multiple-Valued Logic Approach for a Systolic^2 AB Circuit in Galois Field," ismvl, pp.88-93, 35th International Symposium on Multiple-Valued Logic (ISMVL'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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