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35th International Symposium on Multiple-Valued Logic (ISMVL'05)
Multiple-Valued Duplex Asynchronous Data Transfer Scheme for Interleaving in LDPC Decoders
University of Calgary, Canada
May 19-May 21
ISBN: 0-7695-2336-6
Naoya Onizawa, Tohoku University, Japan
Akira Mochizuki, Tohoku University, Japan
Takahiro Hanyu, Tohoku University, Japan
Vincent C. Gaudet, University of Alberta, Edmonton, Canada
A novel duplex asynchronous data-transfer scheme based on multiple-valued encoding is proposed for interleaving in Low-Density Parity-Check (LDPC) decoders, where high-throughput interleavers between variable and check nodes without clock-distribution problems are highly advantageous. Since control signals and data from mutual nodes are multiplexed using a multi-level dual-rail codeword, the number of communication steps can be greatly reduced, which results in high-speed communication without any additional wires. The hardware is simply implemented by utilizing a multiple-valued current-mode circuit because all the information can be superposed on the same line. The advantages of the proposed asynchronous data-transfer scheme are discussed in comparison with corresponding synchronous and conventional asynchronous schemes.
Citation:
Naoya Onizawa, Akira Mochizuki, Takahiro Hanyu, Vincent C. Gaudet, "Multiple-Valued Duplex Asynchronous Data Transfer Scheme for Interleaving in LDPC Decoders," ismvl, pp.138-143, 35th International Symposium on Multiple-Valued Logic (ISMVL'05), 2005
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