35th International Symposium on Multiple-Valued Logic (ISMVL'05) Hardware to Compute Walsh Coefficients University of Calgary, Canada May 19-May 21 ISBN: 0-7695-2336-6
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISMVL.2005.19
This paper presents a method to compute a fragment of the Walsh coefficients of logic functions using hardware. First, it introduces the Walsh transformation tree, and shows a method to compute Walsh coefficients using the Walsh transformation tree. Next, it shows the hardware realization for the Walsh tree. The amount of hardware to compute a coefficient and the entire coefficients are O(2^n ) and O(n^2 • 2^n ), respectively. FPGA implementations show their feasibility up to n = 14. The FPGA realization is at least 1253 times faster than a software implementation on a microprocessor for n = 14.
Citation:
Yukihiro Iguchi, Tsutomu Sasao, "Hardware to Compute Walsh Coefficients," ismvl, pp.75-81, 35th International Symposium on Multiple-Valued Logic (ISMVL'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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