34th International Symposium on Multiple-Valued Logic (ISMVL'04) Algorithms for Taylor Expansion Diagrams University of Toronto, Toronto, Canada May 19-May 22 ISBN: 0-7695-2130-4
The ever increasing size of integrated circuits results in large problem sizes during synthesis and verification of such designs. Recently Taylor Expansion Diagrams (TEDs) were introduced as a data structure to cope with large problem instances. TEDs allow to exploit high level information in the representation of functions. In this paper the basic TED operations are analyzed from a complexity point of view. Suggestions for optimizations of the originally proposed algorithms are made.
Citation:
Goerschwin Fey, Rolf Drechsler, Maciej Ciesielski, "Algorithms for Taylor Expansion Diagrams," ismvl, pp.235-240, 34th International Symposium on Multiple-Valued Logic (ISMVL'04), 2004 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||