Experimental and Simulation Studies of Single-Electron-Transistor-Based Multiple-Valued Logic

I
ISMVL
2003
33rd International Symposium on Multiple-Valued Logic
Abstract - Experimental and Simulation Studies of Single-Electron-Transistor-Based Multiple-Valued Logic

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	Similar Articles Articles by Hiroshi Inokawa Articles by Yasuo Takahashi

33rd International Symposium on Multiple-Valued Logic

Tokyo, Japan

May 16-May 19

ISBN: 0-7695-1918-0

	ASCII Text	x
	Hiroshi Inokawa, Yasuo Takahashi, "Experimental and Simulation Studies of Single-Electron-Transistor-Based Multiple-Valued Logic," Multiple-Valued Logic, IEEE International Symposium on, pp. 259, 33rd International Symposium on Multiple-Valued Logic, 2003.

	BibTex	x
	@article{ 10.1109/ISMVL.2003.1201415, author = {Hiroshi Inokawa and Yasuo Takahashi}, title = {Experimental and Simulation Studies of Single-Electron-Transistor-Based Multiple-Valued Logic}, journal ={Multiple-Valued Logic, IEEE International Symposium on}, volume = {0}, year = {2003}, issn = {0195-623X}, pages = {259}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISMVL.2003.1201415}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Multiple-Valued Logic, IEEE International Symposium on TI - Experimental and Simulation Studies of Single-Electron-Transistor-Based Multiple-Valued Logic SN - 0195-623X SP EP A1 - Hiroshi Inokawa, A1 - Yasuo Takahashi, PY - 2003 KW - null VL - 0 JA - Multiple-Valued Logic, IEEE International Symposium on ER -

Hiroshi Inokawa, NTT Corporation

Yasuo Takahashi, NTT Corporation

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISMVL.2003.1201415

Periodic drain current-gate voltage characteristics of single-electron transistors (SETs) were utilized to construct basic components of multiple-valued logic (MVL), such as a universal literal gate and a quantizer. In order to supplement the small gain and the small applicable voltage of the SET, hybrid SET-MOSFET scheme is proposed and demonstrated experimentally using CMOS-compatible pattern-dependent oxidation (PADOX) technology. We also succeeded in reproducing the results using a SPICE circuit simulator with a compact analytical SET model, and estimated the performance of the proposed MVL.

Citation:

Hiroshi Inokawa, Yasuo Takahashi, "Experimental and Simulation Studies of Single-Electron-Transistor-Based Multiple-Valued Logic," ismvl, pp.259, 33rd International Symposium on Multiple-Valued Logic, 2003

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