Evolutionary Methods in the Design of Quaternery Digital Circuits

I
ISMVL
1998
The 28th International Symposium on Multiple-Valued Logic
Abstract - Evolutionary Methods in the Design of Quaternery Digital Circuits

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The 28th International Symposium on Multiple-Valued Logic

Fukuoka, Japan

May 27-May 29

ISBN: 0-8186-8371-6

	ASCII Text	x
	C. Moraga, W. Wang, "Evolutionary Methods in the Design of Quaternery Digital Circuits," Multiple-Valued Logic, IEEE International Symposium on, pp. 89, The 28th International Symposium on Multiple-Valued Logic, 1998.

	BibTex	x
	@article{ 10.1109/ISMVL.1998.679309, author = {C. Moraga and W. Wang}, title = {Evolutionary Methods in the Design of Quaternery Digital Circuits}, journal ={Multiple-Valued Logic, IEEE International Symposium on}, volume = {0}, year = {1998}, issn = {0195-623X}, pages = {89}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISMVL.1998.679309}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Multiple-Valued Logic, IEEE International Symposium on TI - Evolutionary Methods in the Design of Quaternery Digital Circuits SN - 0195-623X SP EP A1 - C. Moraga, A1 - W. Wang, PY - 1998 VL - 0 JA - Multiple-Valued Logic, IEEE International Symposium on ER -

C. Moraga

W. Wang

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISMVL.1998.679309

Citation:

C. Moraga, W. Wang, "Evolutionary Methods in the Design of Quaternery Digital Circuits," ismvl, pp.89, The 28th International Symposium on Multiple-Valued Logic, 1998

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