M. Morisue, J. Endo, T. Morooka, N. Shimizu, M. Sakamoto, "A Josephson Ternary Memory Circuit," Multiple-Valued Logic, IEEE International Symposium on, pp. 19, The 28th International Symposium on Multiple-Valued Logic, 1998.

@article{ 10.1109/ISMVL.1998.679270,
author = {M. Morisue and J. Endo and T. Morooka and N. Shimizu and M. Sakamoto},
title = {A Josephson Ternary Memory Circuit},
journal ={Multiple-Valued Logic, IEEE International Symposium on},
volume = {0},
year = {1998},
issn = {0195-623X},
pages = {19},
doi = {http://doi.ieeecomputersociety.org/10.1109/ISMVL.1998.679270},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}

TY - CONF
JO - Multiple-Valued Logic, IEEE International Symposium on
TI - A Josephson Ternary Memory Circuit
SN - 0195-623X
SP
EP
A1 - M. Morisue,
A1 - J. Endo,
A1 - T. Morooka,
A1 - N. Shimizu,
A1 - M. Sakamoto,
PY - 1998
VL - 0
JA - Multiple-Valued Logic, IEEE International Symposium on
ER -