Eighth IEEE International Symposium on Multimedia (ISM'06) San Diego, CA December 11-December 13 ISBN: 0-7695-2746-9
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISM.2006.82
This work presents a real-time demonstrator system for the VSP1 Tile. The complete 8-way SIMD VSP1 Tile is implemented on the demonstration platform based on the Xilinx Virtex2 XC2V8000 FPGA chip. The application running on a VSP1 Tile is spatial upscaling. This is a challenging application since it is based on a pixel-based algorithm using content adaptive filtering. The FPGA running on 25 MHz is capable of achieving 17.3 fps for input sequence (320*192) producing four times bigger output sequence (640*384).
Citation:
Aleksandar Beric, Carlos Alba Pinto, "HiveFlex Video VSP1 Demonstration," ism, pp.783-784, Eighth IEEE International Symposium on Multimedia (ISM'06), 2006 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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