2008 International Symposiums on Information Processing
FPGA Implementation of an Adaptive Noise Canceller
May 23-May 25
ISBN: 978-0-7695-3151-9
This paper proposes an FPGA implementation of an Adaptive Noise Canceller using the Least Mean Square (LMS) algorithm. The hardware architecture is synthesized using the Xilinx Spartan-3e Starter Kit as the target board. The experimental result of the hardware implementation shows the performance of LMS algorithm under different conditions and the feasibility of our architecture. A comparison between hardware and pure software implementation is then made with different filter taps.
Index Terms:
field programmable gate array (FPGA), least mean square (LMS) filtering, hardware implementation
Citation:
Tian Lan, Jinlin Zhang, "FPGA Implementation of an Adaptive Noise Canceller," isip, pp.553-558, 2008 International Symposiums on Information Processing, 2008