Sixth International Conference on Intelligent Systems Design and Applications (ISDA'06) Volume 3 Neural Network Approach for Multiple Fault Test of Digital Circuit Jinan, China October 16-October 18 ISBN: 0-7695-2528-8
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISDA.2006.32
A new approach for detecting multiple faults in digital circuits is presented in this paper, which uses neural network technique to generate the test vectors and to diagnose the multiple faults. First of all, the optimal neural network model corresponding to an arbitrary digital circuit is used. For a logic circuit with m inputs and n outputs, the optimal neural networks having m+n neurons can represent the logic function of the circuit. Secondly, the test vectors of multiple faults in the circuit are obtained by using evolutionary strategies to compute the minimum energy states of the optimal neural network. Thirdly, the multi-layer feed forward network and back propagation algorithm are used to diagnose the multiple faults in the circuit. The design of both network configurations and samples patterns are given in detail. Experimental results show that the approaches proposed in this paper are effective for detecting and diagnosing multiple faults in digital circuits.
Citation:
Pan Zhongliang, Chen Ling, Liu Shouqiang, Zhang Guangzhao, "Neural Network Approach for Multiple Fault Test of Digital Circuit," isda, vol. 3, pp.24-29, Sixth International Conference on Intelligent Systems Design and Applications (ISDA'06) Volume 3, 2006 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||