Time randomization method is an effective way to counteract Differential Power Analysis attack. By moving the cryptographic operations randomly in the time domain, this method could provide temporal shift to the power curves. This paper proposed an architecture for time randomization of AES. By randomly inserting registers among cryptographic modules, the architecture could change the physical location of registers through dynamical reconfiguration. The design is realized using Altera’s FPGA. Synthesis, placement and routing of the design have been accomplished on 0.18μm CMOS technology. The result proves that the propagation time of the critical path is 4.57ns. Furthermore, the architecture could effectively counteract Differential Power Analysis.