An opto-electronic three-stage packet switch architecture is described that plays to the strengths of electronics as a memory technology and to photonics as a communications technology whilst accommodating the relatively slow reconfiguration of current transparent photonic switch technology. The configuration of the photonic centre stage is found by solving an edge-colouring problem on a bipartite graph defined by the traffic. This is simple to implement and the calculation need be repeated only if there are persistent variations in the statistical pattern of the arriving traffic. A major bottleneck is removed by dispensing with a per-time slot scheduler; at the price of only a modest spatial speed-up, which is easy to provide with photonic technology. The architecture and method have been verified by simulation using simple traffic models that capture the non-stationary and bursty nature of real traffic.