33rd International Symposium on Computer Architecture (ISCA'06) Improving Cost, Performance, and Security of Memory Encryption and Authentication Boston, Massachusetts June 17-June 21 ISBN: 0-7695-2608-X
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISCA.2006.22
Protection from hardware attacks such as snoopers and mod chips has been receiving increasing attention in computer architecture. This paper presents a new combined memory encryption/authentication scheme. Our new split counters for counter-mode encryption simultaneously eliminate counter overflow problems and reduce per-block counter size, and we also dramatically improve authentication performance and security by using the Galois/Counter Mode of operation (GCM), which leverages counter-mode encryption to reduce authentication latency and overlap it with memory accesses. Our results indicate that the split-counter scheme has a negligible overhead even with a small (32KB) counter cache and using only eight counter bits per data block. The combined encryption/authentication scheme has an IPC overhead of 5% on average across SPEC CPU 2000 benchmarks, which is a significant improvement over the 20% overhead of existing encryption/authentication schemes.
Citation:
Chenyu Yan, Daniel Englender, Milos Prvulovic, Brian Rogers, Yan Solihin, "Improving Cost, Performance, and Security of Memory Encryption and Authentication," isca, pp.179-190, 33rd International Symposium on Computer Architecture (ISCA'06), 2006 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||