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33rd International Symposium on Computer Architecture (ISCA'06)
Bulk Disambiguation of Speculative Threads in Multiprocessors
Boston, Massachusetts
June 17-June 21
ISBN: 0-7695-2608-X
Luis Ceze, University of Illinois at Urbana-Champaign
James Tuck, University of Illinois at Urbana-Champaign
Josep Torrellas, University of Illinois at Urbana-Champaign
Calin Cascaval, IBM T.J. Watson Research Center

Transactional Memory (TM), Thread-Level Speculation (TLS), and Checkpointed multiprocessors are three popular architectural techniques based on the execution of multiple, cooperating speculative threads. In these environments, correctly maintaining data dependences across threads requires mechanisms for disambiguating addresses across threads, invalidating stale cache state, and making committed state visible. These mechanisms are both conceptually involved and hard to implement.

In this paper, we present Bulk, a novel approach to simplify these mechanisms. The idea is to hash-encode a thread?s access information in a concise signature, and then support in hardware signature operations that efficiently process sets of addresses. Such operations implement the mechanisms described. Bulk operations are inexact but correct, and provide substantial conceptual and implementation simplicity. We evaluate Bulk in the context of TLS using SPECint2000 codes and TM using multithreaded Java workloads. Despite its simplicity, Bulk has competitive performance with more complex schemes. We also find that signature configuration is a key design parameter.

Citation:
Luis Ceze, James Tuck, Josep Torrellas, Calin Cascaval, "Bulk Disambiguation of Speculative Threads in Multiprocessors," isca, pp.227-238, 33rd International Symposium on Computer Architecture (ISCA'06), 2006
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