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29th Annual International Symposium on Computer Architecture (ISCA'02)
Using a User-Level Memory Thread for Correlation Prefetching
Anchorage, Alaska
May 25-May 29
ISBN: 0-7695-1605-X
Yan Solihin, University of Illinois at Urbana-Champaign
Josep Torrellas, University of Illinois at Urbana-Champaign
Jaejin Lee, Michigan State University
This paper introduces the idea of using a User-Level Memory Thread (ULMT) for correlation prefetching. In this approach, a user thread runs on a general-purpose processor in main memory, either in the memory controller chip or in a DRAM chip. The thread performs correlation prefetching in software, sending the prefetched data into the L2 cache of the main processor.This approach requires minimal hardware beyond the memory processor: the correlation table is a software data structure that resides in main memory, while the main processor only needs a few modifications to its L2 cache so it can accept incoming prefetches. In addition, the approach is very flexible, as the prefetching algorithm can be customized on a per-application basis. Finally, it has wide usability, as it can effectively prefetch even for irregular applications.Our simulation results show that, with a new organization of the correlation table and a new correlation prefetching algorithm, our scheme delivers very promising results. The average speedup on nine mostly-irregular applications is 1.32. Moreover, our scheme works well in combination with a conventional processor-side prefetcher, in which case the average speedup increases to 1.46. Finally, customization of the prefetching algorithm further increases the average speedup to 1.53.
Index Terms:
data prefetching, intelligent memory, processing-in-memory, computer architecture, correlation prefetching, memory hierarchies, caches, threads
Citation:
Yan Solihin, Josep Torrellas, Jaejin Lee, "Using a User-Level Memory Thread for Correlation Prefetching," isca, pp.0171, 29th Annual International Symposium on Computer Architecture (ISCA'02), 2002
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