Dynamically reconfigurable cache architecture using adaptive block allocation policy

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Proceedings 20th IEEE International Parallel & Distributed Processing Symposium

Rhodes Island, Greece

April 25-April 29

ISBN: 1-4244-0054-6

	ASCII Text	x
	M.B. Carvalho, L.F.W. Goes, C.A.P.S. Martins, "Dynamically reconfigurable cache architecture using adaptive block allocation policy," Parallel and Distributed Processing Symposium, International, pp. 230, Proceedings 20th IEEE International Parallel & Distributed Processing Symposium, 2006.

	BibTex	x
	@article{ 10.1109/IPDPS.2006.1639487, author = {M.B. Carvalho and L.F.W. Goes and C.A.P.S. Martins}, title = {Dynamically reconfigurable cache architecture using adaptive block allocation policy}, journal ={Parallel and Distributed Processing Symposium, International}, volume = {0}, year = {2006}, isbn = {1-4244-0054-6}, pages = {230}, doi = {http://doi.ieeecomputersociety.org/10.1109/IPDPS.2006.1639487}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Parallel and Distributed Processing Symposium, International TI - Dynamically reconfigurable cache architecture using adaptive block allocation policy SN - 1-4244-0054-6 SP EP A1 - M.B. Carvalho, A1 - L.F.W. Goes, A1 - C.A.P.S. Martins, PY - 2006 KW - cache response time KW - dynamically reconfigurable cache architecture KW - adaptive block allocation policy KW - set associative configuration KW - cache miss ratio VL - 0 JA - Parallel and Distributed Processing Symposium, International ER -

M.B. Carvalho, Computational&Digital Syst. Lab., Pontifical Catholic Univ. of Minas Gerais, Belo Horizonte, Brazil

L.F.W. Goes, Computational&Digital Syst. Lab., Pontifical Catholic Univ. of Minas Gerais, Belo Horizonte, Brazil

C.A.P.S. Martins, Computational&Digital Syst. Lab., Pontifical Catholic Univ. of Minas Gerais, Belo Horizonte, Brazil

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IPDPS.2006.1639487

In this paper, we present a dynamically reconfigurable cache architecture using adaptive block allocation policy analyzed by means of simulation. Our main objectives are: to propose a reconfigurable cache architecture and to propose, implement and analyze the performance of an adaptive cache block allocation policy. First, we present a proposal of the reconfigurable cache architecture that can adapt according to the workload. Then we present our adaptive policy and do some performance tests comparing our cache architecture with some set associative configurations. In these tests, we use some traces from BYU Trace Distribution Center of SPEC 2000 Benchmark. Finally, we analyze the results based on some metrics like cache miss ratio, response time, etc.

Index Terms:

cache response time, dynamically reconfigurable cache architecture, adaptive block allocation policy, set associative configuration, cache miss ratio

Citation:

M.B. Carvalho, L.F.W. Goes, C.A.P.S. Martins, "Dynamically reconfigurable cache architecture using adaptive block allocation policy," ipdps, pp.230, Proceedings 20th IEEE International Parallel & Distributed Processing Symposium, 2006

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