19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 Accelerating Scientific Applications with the SRC-6 Reconfigurable Computer: Methodologies and Analysis Denver, Colorado April 04-April 08 ISBN: 0-7695-2312-9
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IPDPS.2005.75
Reconfigurable computing offers the promise of performing computations in hardware to increase performance and efficiency while retaining much of the flexibility of a software solution. Recently, the capacities of reconfigurable computing devices, like field programmable gate arrays, have risen to levels that make it possible to execute 64b floating-point operations. SRC Computers has designed the SRC-6 MAPstation to blend the benefits of commodity processors with the benefits of reconfigurable computing. In this paper, we describe our effort to accelerate the performance of several scientific applications on the SRC-6. We describe our methodology, analysis, and results. Our early evaluation demonstrates that the SRC-6 provides a unique software stack that is applicable to many scientific solutions and our experiments reveal the performance benefits of the system.
Index Terms:
Reconfigurable Computing, Scientific Applications, Performance Analysis
Citation:
Melissa C. Smith, Jeffery S. Vetter, Xuejun Liang, "Accelerating Scientific Applications with the SRC-6 Reconfigurable Computer: Methodologies and Analysis," ipdps, vol. 4, pp.157b, 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3, 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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