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19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Papers
Runtime Empirical Selection of Loop Schedulers on Hyperthreaded SMPs
Denver, Colorado
April 04-April 08
ISBN: 0-7695-2312-9
Yun Zhang, University of Toronto, Canada
Michael Voss, University of Toronto, Canada
Hyperthreaded (HT) and simultaneous multithreaded (SMT) processors are now available in commodity workstations and servers. This technology is designed to increase throughput by executing multiple concurrent threads on a single physical processor. These multiple threads share the processor's functional units and on-chip memory hierarchy in an attempt to make better use of idle resources. Most OpenMP applications have been written assuming an Symmetric Multiprocessor (SMP), not an SMT, model. Threads executing on the same physical processor have interactions on data locality and resource sharing that do not occur on traditional SMPs. This work focuses on tuning the behavior of OpenMP applications executing on SMPs with SMT processors. We propose two adaptive loop schedulers that determine effective hierarchical schedulers for individual parallel loops. We compare the performance of our two proposed schedulers against several standard schedulers and the per-region adaptive scheduler proposed by Zhang et al. using the SPEC and NAS OpenMP benchmark suites. We show that both of our proposed schedulers outperform all other schedulers on average, and increase speedup on average by over 25% when all thread contexts are used.
Citation:
Yun Zhang, Michael Voss, "Runtime Empirical Selection of Loop Schedulers on Hyperthreaded SMPs," ipdps, vol. 1, pp.44b, 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Papers, 2005
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