Grayscale electron-beam lithography is one of the techniques used in transferring circuit patterns with multi-level structures onto substrates. The proximity effect caused by electron scattering imposes a severe limitation on the ultimate spatial resolution attainable by E-beam lithography. Therefore, proximity effect correction is essential particularly for fine-feature, high-density circuit patterns. One difficulty is that it is extremely time-consuming due to the intensive computation required in the correction procedure and a large size of circuit data to be processed. Hence, it is an ideal candidate for distributed computing where the otherwise-unused CPU cycles of a number of computers on a network (cluster) can be efficiently utilized. In this paper, optimization of the distributed grayscale proximity effect correction procedure previously developed is addressed for minimizing the correction time. Also, a different circuit partitioning approach (localized partitioning) is considered.