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19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 14
Memory In Processor-Supercomputer On a Chip: Processor Design and Execution Semantics for Massive Single-Chip Performance
Denver, Colorado
April 04-April 08
ISBN: 0-7695-2312-9
ASCII Text
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N. Venkateswaran, Arrvindh Shriraman, Niranjan Soundararajan, "Memory In Processor-Supercomputer On a Chip: Processor Design and Execution Semantics for Massive Single-Chip Performance," Parallel and Distributed Processing Symposium, International, vol. 15, pp. 263b, 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 14, 2005.
 
 
BibTex
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@article{ 10.1109/IPDPS.2005.279,
author = {N. Venkateswaran and Arrvindh Shriraman and Niranjan Soundararajan},
title = {Memory In Processor-Supercomputer On a Chip: Processor Design and Execution Semantics for Massive Single-Chip Performance},
journal ={Parallel and Distributed Processing Symposium, International},
volume = {15},
year = {2005},
issn = {1530-2075},
pages = {263b},
doi = {http://doi.ieeecomputersociety.org/10.1109/IPDPS.2005.279},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Parallel and Distributed Processing Symposium, International
TI - Memory In Processor-Supercomputer On a Chip: Processor Design and Execution Semantics for Massive Single-Chip Performance
SN - 1530-2075
SP
EP
A1 - N. Venkateswaran,
A1 - Arrvindh Shriraman,
A1 - Niranjan Soundararajan,
PY - 2005
KW - null
VL - 15
JA - Parallel and Distributed Processing Symposium, International
ER -
 
N. Venkateswaran, WARAN Research Foundation, Chennai, India
Arrvindh Shriraman, University of Rochester
Niranjan Soundararajan, Duke University
The MIP S.C.O.C was designed to overcome the Von-Neumann bottleneck and develop massive on-chip parallelism to achieve Teraflop scale single chip performance. We case study here a specific 2 MB MIP node that has a 128 bit datapath. This paper also specifies the technological reqirements and discusses the implementation strategy to support the feasibility of the project. We develop the ISA format and preview the hardware compiler COS, that will map applications and schedule the instructions on the MIP S.C.O.C. We then discuss the library specifications and COS-HLF unit interface. We develop the scalable pyramid cluster to accomodate massive node performance. We discuss briefly the programming model and an application execution to demonstrate the scalability.
Citation:
N. Venkateswaran, Arrvindh Shriraman, Niranjan Soundararajan, "Memory In Processor-Supercomputer On a Chip: Processor Design and Execution Semantics for Massive Single-Chip Performance," ipdps, vol. 15, pp.263b, 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 14, 2005
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