Low-Power Reconfigurable VLSI Architecture for the Implementation of FIR Filters

I
IPDPS
2005
19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3
Abstract - Low-Power Reconfigurable VLSI Architecture for the Implementation of FIR Filters

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	Similar Articles Articles by Evangelos F. Stefatos Articles by Han Wei Articles by Tughrul Arslan Articles by Robert Thomson

19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3

Denver, Colorado

April 04-April 08

ISBN: 0-7695-2312-9

	ASCII Text	x
	Evangelos F. Stefatos, Han Wei, Tughrul Arslan, Robert Thomson, "Low-Power Reconfigurable VLSI Architecture for the Implementation of FIR Filters," Parallel and Distributed Processing Symposium, International, vol. 4, pp. 168b, 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3, 2005.

	BibTex	x
	@article{ 10.1109/IPDPS.2005.271, author = {Evangelos F. Stefatos and Han Wei and Tughrul Arslan and Robert Thomson}, title = {Low-Power Reconfigurable VLSI Architecture for the Implementation of FIR Filters}, journal ={Parallel and Distributed Processing Symposium, International}, volume = {4}, year = {2005}, issn = {1530-2075}, pages = {168b}, doi = {http://doi.ieeecomputersociety.org/10.1109/IPDPS.2005.271}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Parallel and Distributed Processing Symposium, International TI - Low-Power Reconfigurable VLSI Architecture for the Implementation of FIR Filters SN - 1530-2075 SP EP A1 - Evangelos F. Stefatos, A1 - Han Wei, A1 - Tughrul Arslan, A1 - Robert Thomson, PY - 2005 KW - null VL - 4 JA - Parallel and Distributed Processing Symposium, International ER -

Evangelos F. Stefatos, The University of Edinburgh, UK

Han Wei, The University of Edinburgh, UK

Tughrul Arslan, The University of Edinburgh, UK

Robert Thomson, The University of Edinburgh, UK

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IPDPS.2005.271

This paper presents a custom reconfigurable VLSI architecture that is tailored for the implementation of low-power, medium/high order, digital finite impulse response (FIR) filters. These are realized within a reconfigurable array that consists of heterogeneous, programmable, arithmetic-logic units. The reconfigurable design is based on the primitive operator design (POF) technique. The concept of a genetic algorithm (GA) is introduced, which utilizes a randix-4, 256-point fast-fourier-transform (FFT) to calculate the frequency response of the evolved filters. The results related to the performance, physical-area and power consumption make this architecture very competitive in comparison with other industrial, general purpose FPGAs.

Citation:

Evangelos F. Stefatos, Han Wei, Tughrul Arslan, Robert Thomson, "Low-Power Reconfigurable VLSI Architecture for the Implementation of FIR Filters," ipdps, vol. 4, pp.168b, 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3, 2005

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