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19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3
Generic Design Space Exploration for Reconfigurable Architectures
Denver, Colorado
April 04-April 08
ISBN: 0-7695-2312-9
Lilian Bossuet, Universit? de Bretagne Sud, Lorient, France
Guy Gogniat, Universit? de Bretagne Sud, Lorient, France
Jean-Luc Philippe, Universit? de Bretagne Sud, Lorient, France
We propose in this paper an original design space exploration method for reconfigurable architectures adapted to fine and coarse grain resources. The exploration flow deals with communication hierarchical distribution and processing resources use rate for the architecture under exploration. With this information, designer can explore the architectural design space to define a power-efficient architecture. Exploration results for image computing and cryptography applications are provided to demonstrate the efficiency of the method.
Citation:
Lilian Bossuet, Guy Gogniat, Jean-Luc Philippe, "Generic Design Space Exploration for Reconfigurable Architectures," ipdps, vol. 4, pp.163a, 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3, 2005
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