Modern internet and telephone switches consist of numerous VLSI-circuits operating at high frequencies to handle high bandwidths. It is beyond question that such systems must contain mechanisms making them reliable through fault-detection or fault-tolerance. For monetary reasons, one or multiple Field Programmable Gate Arrays (FPGAs) are used in modern Application Specific Integrated Circuit (ASIC) development systems before production. Hardware manufacturers have a strong focus on quick fault-injection to verify and validate the correct function of such a (faulttolerant) system. However, current FPGA-based fault injection schemes do not consider delay faults. In this paper we present an extension to traditional FPGA fault injection schemes without any additional hardware for fixed and small hardware overhead for dynamic phase shifting. By using digital clock managers (DCMs), we are able to inject delay faults very fast through phase-shift variation of the clock without reconfiguring the FPGA.