DAGGER: A Novel Generic Methodology for FPGA Bitstream Generation and Its Software Tool Implementation

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19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3

Denver, Colorado

April 04-April 08

ISBN: 0-7695-2312-9

	ASCII Text	x
	K. Siozios, G. Koutroumpezis, K. Tatas, D. Soudris, A. Thanailakis, "DAGGER: A Novel Generic Methodology for FPGA Bitstream Generation and Its Software Tool Implementation," Parallel and Distributed Processing Symposium, International, vol. 4, pp. 165b, 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3, 2005.

	BibTex	x
	@article{ 10.1109/IPDPS.2005.158, author = {K. Siozios and G. Koutroumpezis and K. Tatas and D. Soudris and A. Thanailakis}, title = {DAGGER: A Novel Generic Methodology for FPGA Bitstream Generation and Its Software Tool Implementation}, journal ={Parallel and Distributed Processing Symposium, International}, volume = {4}, year = {2005}, issn = {1530-2075}, pages = {165b}, doi = {http://doi.ieeecomputersociety.org/10.1109/IPDPS.2005.158}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Parallel and Distributed Processing Symposium, International TI - DAGGER: A Novel Generic Methodology for FPGA Bitstream Generation and Its Software Tool Implementation SN - 1530-2075 SP EP A1 - K. Siozios, A1 - G. Koutroumpezis, A1 - K. Tatas, A1 - D. Soudris, A1 - A. Thanailakis, PY - 2005 KW - FPGA KW - bitstream generator KW - partial KW - runtime KW - reconfiguration KW - tool development VL - 4 JA - Parallel and Distributed Processing Symposium, International ER -

K. Siozios, Democritus University of Thrace, Greece

G. Koutroumpezis, Democritus University of Thrace, Greece

K. Tatas, Democritus University of Thrace, Greece

D. Soudris, Democritus University of Thrace, Greece

A. Thanailakis, Democritus University of Thrace, Greece

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IPDPS.2005.158

A novel bitstream generation algorithm and its software implementation are introduced. Although this tool was developed for the configuration of AMDREL FPGA reconfigurable platform, it could be used to program any other compatible device. This tool is the only one known academic implementation for FPGA configuration with such features. Among them are the run-time-, partial- and dynamic-reconfiguration, the memory management, the bitstream compression and encryption, the read-back technique, the bitstream reallocation, the used low-power techniques as well as the Graphical User Interface.

Index Terms:

FPGA, bitstream generator, partial, runtime, reconfiguration, tool development

Citation:

K. Siozios, G. Koutroumpezis, K. Tatas, D. Soudris, A. Thanailakis, "DAGGER: A Novel Generic Methodology for FPGA Bitstream Generation and Its Software Tool Implementation," ipdps, vol. 4, pp.165b, 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3, 2005

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