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18th International Parallel and Distributed Processing Symposium (IPDPS'04) - Workshop 3
An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development
Santa Fe, New Mexico
April 26-April 30
ISBN: 0-7695-2132-0
ASCII Text
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V. Kalenteridis, H. Pournara, K. Siozios, K. Tatas, G. Koytroympezis, I. Pappas, S. Nikolaidis, S. Siskos, D. J. Soudris, A. Thanailakis, "An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development," Parallel and Distributed Processing Symposium, International, vol. 4, pp. 138a, 18th International Parallel and Distributed Processing Symposium (IPDPS'04) - Workshop 3, 2004.
 
 
BibTex
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@article{ 10.1109/IPDPS.2004.1303112,
author = {V. Kalenteridis and H. Pournara and K. Siozios and K. Tatas and G. Koytroympezis and I. Pappas and S. Nikolaidis and S. Siskos and D. J. Soudris and A. Thanailakis},
title = {An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development},
journal ={Parallel and Distributed Processing Symposium, International},
volume = {4},
year = {2004},
isbn = {0-7695-2132-0},
pages = {138a},
doi = {http://doi.ieeecomputersociety.org/10.1109/IPDPS.2004.1303112},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Parallel and Distributed Processing Symposium, International
TI - An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development
SN - 0-7695-2132-0
SP
EP
A1 - V. Kalenteridis,
A1 - H. Pournara,
A1 - K. Siozios,
A1 - K. Tatas,
A1 - G. Koytroympezis,
A1 - I. Pappas,
A1 - S. Nikolaidis,
A1 - S. Siskos,
A1 - D. J. Soudris,
A1 - A. Thanailakis,
PY - 2004
KW - Low Power FPGA interconnect architecture
KW - CLB Architecture
KW - Graphical User Interface
VL - 4
JA - Parallel and Distributed Processing Symposium, International
ER -
 
V. Kalenteridis, Aristotle University of Thessaloniki
H. Pournara, Aristotle University of Thessaloniki
K. Siozios, Democritus University of Thrace
K. Tatas, Democritus University of Thrace
G. Koytroympezis, Democritus University of Thrace
I. Pappas, Aristotle University of Thessaloniki
S. Nikolaidis, Aristotle University of Thessaloniki
S. Siskos, Aristotle University of Thessaloniki
D. J. Soudris, Democritus University of Thrace
A. Thanailakis, Democritus University of Thrace
A complete system for the implementation of digital logic in a fine-grain reconfigurable platform is introduced. The system is composed of two parts: The fine-grain reconfigurable hardware platform (FPGA) on which the logic is implemented and the set of CAD tools for mapping logic to the FPGA platform. The novel energy-efficient FPGA architecture was designed and simulated in STM 0.18?m CMOS technology. Concerning the tool flow, each tool can operate as a standalone program as well as part of a complete design framework, composed by existing and new tools.
Index Terms:
Low Power FPGA interconnect architecture, CLB Architecture, Graphical User Interface
Citation:
V. Kalenteridis, H. Pournara, K. Siozios, K. Tatas, G. Koytroympezis, I. Pappas, S. Nikolaidis, S. Siskos, D. J. Soudris, A. Thanailakis, "An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development," ipdps, vol. 4, pp.138a, 18th International Parallel and Distributed Processing Symposium (IPDPS'04) - Workshop 3, 2004
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