An FPGA Implementation of a Flexible, Parallel Image Processing Architecture Suitable for Embedded Vision Systems

I
IPDPS
2003
International Parallel and Distributed Processing Symposium (IPDPS'03)
Abstract - An FPGA Implementation of a Flexible, Parallel Image Processing Architecture Suitable for Embedded Vision Systems

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International Parallel and Distributed Processing Symposium (IPDPS'03)

Nice, France

April 22-April 26

ISBN: 0-7695-1926-1

	ASCII Text	x
	Stephanie McBader, Peter Lee, "An FPGA Implementation of a Flexible, Parallel Image Processing Architecture Suitable for Embedded Vision Systems," Parallel and Distributed Processing Symposium, International, pp. 228a, International Parallel and Distributed Processing Symposium (IPDPS'03), 2003.

	BibTex	x
	@article{ 10.1109/IPDPS.2003.1213415, author = {Stephanie McBader and Peter Lee}, title = {An FPGA Implementation of a Flexible, Parallel Image Processing Architecture Suitable for Embedded Vision Systems}, journal ={Parallel and Distributed Processing Symposium, International}, volume = {0}, year = {2003}, issn = {1530-2075}, pages = {228a}, doi = {http://doi.ieeecomputersociety.org/10.1109/IPDPS.2003.1213415}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Parallel and Distributed Processing Symposium, International TI - An FPGA Implementation of a Flexible, Parallel Image Processing Architecture Suitable for Embedded Vision Systems SN - 1530-2075 SP EP A1 - Stephanie McBader, A1 - Peter Lee, PY - 2003 KW - null VL - 0 JA - Parallel and Distributed Processing Symposium, International ER -

Stephanie McBader, NeuriCam S.p.A,

Peter Lee, University of Kent at Canterbury

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IPDPS.2003.1213415

This paper describes the design of a programmable parallel architecture that is to be used for signal preprocessing in intelligent embedded vision systems. The architecture has been implemented and tested using a Celoxica RC1000 Prototyping Platform with a Xilinx XCV2000E FPGA. The system operates at a clock rate of 50 MHz and can perform preprocessing functions such as filtering, correlation and transformation on an image of 256x256 pixels at up to 667 frames/s.

Citation:

Stephanie McBader, Peter Lee, "An FPGA Implementation of a Flexible, Parallel Image Processing Architecture Suitable for Embedded Vision Systems," ipdps, pp.228a, International Parallel and Distributed Processing Symposium (IPDPS'03), 2003

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