International Parallel and Distributed Processing Symposium (IPDPS'03) The Coherence Predictor Cache: A Resource-Efficient and Accurate Coherence Prediction Infrastructure Nice, France April 22-April 26 ISBN: 0-7695-1926-1
Two-level coherence predictors have shown great promise to reduce coherence overhead in shared memory multiprocessors. However, to be accurate they require a memory overhead that on e.g. a 64-processor machine can be as high as 50%. Based on an application case study consisting of seven applications from SPLASH-2, a first observation made in this paper is that memory blocks subject to coherence activities usually constitute only a small fraction (around 10%) of the entire application footprint. Based on this, we contribute with a new class of resource-efficient coherence predictors that is organized as a cache attached to each memory controller. We show that such a Coherence Predictor Cache (CPC) can provide nearly as effective predictions as if a predictor is associated with every memory block, but needs only 2-7% as many predictors.
Index Terms:
Shared-memory multiprocessors, coherence message prediction, memory overhead, caches
Citation:
Jim Nilsson, Anders Landin, Per Stenström, "The Coherence Predictor Cache: A Resource-Efficient and Accurate Coherence Prediction Infrastructure," ipdps, pp.10a, International Parallel and Distributed Processing Symposium (IPDPS'03), 2003 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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