Security of cryptographic circuits is a major concern. Fault attacks are a mean to obtain critical information with the use of physical disturbance and cryptanalysis. We propose a methodology and a tool to analyse the robustness of circuit under faults induced by a delay. We tested a circuit implementing AES and showed that delay faults can permit to perform known fault attacks.
Citation:
Olivier Faurax, Assia Tria, Laurent Freund, Frederic Bancel, "Robustness of circuits under delay-induced faults : test of AES with the PAFI tool," iolts, pp.185-186, 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007