A C-element Latch Scheme with Increased Transient Fault Tolerance for Asynchronous Circuits

I
IOLTS
2007
13th IEEE International On-Line Testing Symposium (IOLTS 2007)
Abstract - A C-element Latch Scheme with Increased Transient Fault Tolerance for Asynchronous Circuits

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13th IEEE International On-Line Testing Symposium (IOLTS 2007)

Heraklion, Crete, Greece

July 08-July 11

ISBN: 0-7695-2918-6

	ASCII Text	x
	K.T. Gardiner, A. Yakovlev, A. Bystrov, "A C-element Latch Scheme with Increased Transient Fault Tolerance for Asynchronous Circuits," On-Line Testing Symposium, IEEE International, pp. 223-230, 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007.

	BibTex	x
	@article{ 10.1109/IOLTS.2007.5, author = {K.T. Gardiner and A. Yakovlev and A. Bystrov}, title = {A C-element Latch Scheme with Increased Transient Fault Tolerance for Asynchronous Circuits}, journal ={On-Line Testing Symposium, IEEE International}, volume = {0}, year = {2007}, isbn = {0-7695-2918-6}, pages = {223-230}, doi = {http://doi.ieeecomputersociety.org/10.1109/IOLTS.2007.5}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - On-Line Testing Symposium, IEEE International TI - A C-element Latch Scheme with Increased Transient Fault Tolerance for Asynchronous Circuits SN - 0-7695-2918-6 SP223 EP230 A1 - K.T. Gardiner, A1 - A. Yakovlev, A1 - A. Bystrov, PY - 2007 KW - null VL - 0 JA - On-Line Testing Symposium, IEEE International ER -

K.T. Gardiner, University of Newcastle upon Tyne, UK

A. Yakovlev, University of Newcastle upon Tyne, UK

A. Bystrov, University of Newcastle upon Tyne, UK

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IOLTS.2007.5

A technique of constructing dual-rail Muller pipelines tolerant to transient faults is proposed. The pipeline datapath is either an NCL-D or NCL-X circuit. A dedicated controller implements the error recovery protocol, which significantly improves fault tolerance with respect to the earlier Rail Synchronization method. A case study featuring transient fault simulation is presented.

Citation:

K.T. Gardiner, A. Yakovlev, A. Bystrov, "A C-element Latch Scheme with Increased Transient Fault Tolerance for Asynchronous Circuits," iolts, pp.223-230, 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

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