In this paper, a new methodology is proposed to improve digital circuit signal integrity, in the presence of power-supply voltage (VDD) and temperature (T) variations. The underlying principle of the proposed methodology is to introduce on-line additional tolerance, by dynamically controlling the instant of occurrence of the clock edge trigger driving specific memory cells. On-line, dynamic delay insertion in the clock signal driving such memory cells is performed, according to local VDD and/or T variations, using a Dynamic Delay Buffer (DDB) block. The circuit becomes more tolerant to power line and temperature fluctuations, while maintaining at-speed clock rate. Moreover, when clock frequency reduction becomes unavoidable, the methodology improves signal integrity when the disturbances start to occur, allowing time for the clock generator to react and reduce its frequency. Experimental results based on SPICE simulations for two sequential circuits are used to demonstrate the usefulness of the proposed methodology.