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13th IEEE International On-Line Testing Symposium (IOLTS 2007)
Heraklion, Crete, Greece
July 08-July 11
ISBN: 0-7695-2918-6
ASCII Text
x 
 
Costas Argyrides, Dhiraj K. Pradhan, "Highly Reliable Power Aware Memory Design," On-Line Testing Symposium, IEEE International, pp. 189-190, 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007.
 
 
BibTex
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@article{ 10.1109/IOLTS.2007.37,
author = {Costas Argyrides and Dhiraj K. Pradhan},
title = {Highly Reliable Power Aware Memory Design},
journal ={On-Line Testing Symposium, IEEE International},
volume = {0},
year = {2007},
isbn = {0-7695-2918-6},
pages = {189-190},
doi = {http://doi.ieeecomputersociety.org/10.1109/IOLTS.2007.37},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - On-Line Testing Symposium, IEEE International
TI - Highly Reliable Power Aware Memory Design
SN - 0-7695-2918-6
SP189
EP190
A1 - Costas Argyrides,
A1 - Dhiraj K. Pradhan,
PY - 2007
KW - null
VL - 0
JA - On-Line Testing Symposium, IEEE International
ER -
 
Costas Argyrides, University of Bristol, UK
Dhiraj K. Pradhan, University of Bristol, UK
In this paper, an efficient technique for designing RAMs for on chip correction of double errors integrated on H-tree memory architecture is discussed. The reliability of the proposed design is improved by 8X while the Mean Time To Failure is improved 3X while comparing to traditional Hamming codes for a 256Mbits memory chip. The area is sacrificed for these reliability improvements, significant power savings and the performance boost.
Citation:
Costas Argyrides, Dhiraj K. Pradhan, "Highly Reliable Power Aware Memory Design," iolts, pp.189-190, 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
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