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13th IEEE International On-Line Testing Symposium (IOLTS 2007)
Heraklion, Crete, Greece
July 08-July 11
ISBN: 0-7695-2918-6
ASCII Text
x 
 
Fabrice Monteiro, Stanislaw J. Piestrak, Houssein Jaber, Abbas Dandache, "Fault-Secure Interface Between Fault-Tolerant RAM and Transmission Channel Using Systematic Cyclic Codes," On-Line Testing Symposium, IEEE International, pp. 199-200, 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007.
 
 
BibTex
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@article{ 10.1109/IOLTS.2007.32,
author = {Fabrice Monteiro and Stanislaw J. Piestrak and Houssein Jaber and Abbas Dandache},
title = {Fault-Secure Interface Between Fault-Tolerant RAM and Transmission Channel Using Systematic Cyclic Codes},
journal ={On-Line Testing Symposium, IEEE International},
volume = {0},
year = {2007},
isbn = {0-7695-2918-6},
pages = {199-200},
doi = {http://doi.ieeecomputersociety.org/10.1109/IOLTS.2007.32},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - On-Line Testing Symposium, IEEE International
TI - Fault-Secure Interface Between Fault-Tolerant RAM and Transmission Channel Using Systematic Cyclic Codes
SN - 0-7695-2918-6
SP199
EP200
A1 - Fabrice Monteiro,
A1 - Stanislaw J. Piestrak,
A1 - Houssein Jaber,
A1 - Abbas Dandache,
PY - 2007
KW - null
VL - 0
JA - On-Line Testing Symposium, IEEE International
ER -
 
Fabrice Monteiro, University of Metz, France
Stanislaw J. Piestrak, University of Metz, France
Houssein Jaber, University of Metz, France
Abbas Dandache, University of Metz, France
The problem of designing a fault-secure interface between a fault-tolerant RAM memory system and a transmission channel, both protected against errors using cyclic linear error detecting and/or correcting codes is considered. The main idea relies on using the RAM check bits to control the correct operation of the parallel cyclic code encoder, so that the whole interface has no single point of failure.
Citation:
Fabrice Monteiro, Stanislaw J. Piestrak, Houssein Jaber, Abbas Dandache, "Fault-Secure Interface Between Fault-Tolerant RAM and Transmission Channel Using Systematic Cyclic Codes," iolts, pp.199-200, 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
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