13th IEEE International On-Line Testing Symposium (IOLTS 2007) Heraklion, Crete, Greece July 08-July 11 ISBN: 0-7695-2918-6
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IOLTS.2007.29
Current trends in VLSI designs necessitate low power during both normal system operation and testing activity. Traditional Built-in Self Test (BIST) generators rise the power and energy consumption during testing, boosting the need to add low-power solutions to the arsenal of BIST pattern generators. In this work, the utilization of gray code generators is proposed as a low-power BIST solution; more precisely, we propose an algorithm to embed a test pattern into a sequence generated by a gray code generator. Hence, test sets can be embedded into gray sequences.
Index Terms:
Built-In Self Test, Test set embedding, Gray sequences, Low power sequences
Citation:
Ioannis Voyiatzis, "Embedding test patterns into Low-Power BIST sequences," iolts, pp.197-198, 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||